1. Field of the Invention
The present invention relates to methods of fabricating a semiconductor memory device and, more particularly, to methods of fabricating a phase change memory device having a small area of contact.
2. Description of the Related Art
Semiconductor memory devices may be classified as volatile memory devices or non-volatile memory devices, depending on whether data is retained when the power supply is interrupted. The non-volatile memory device has an advantage in that data stored therein is not erased even when the power supply is interrupted. Accordingly, the non-volatile memory device is widely employed in a mobile communication system, a memory card, and so forth.
A flash memory device is widely used as the non-volatile memory device. The flash memory device usually employs memory cells having a stacked gate structure. The stacked gate structure includes a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode which are sequentially stacked on a channel region. A principle of programming and erasing data into and from the flash memory cell employs methods of tunneling charges through the tunnel insulating layer. In order to enhance reliability and program efficiency of the flash memory device, a film quality of the tunnel insulating layer should be improved and a coupling rate of the cell should be increased. However, such tasks as the improvement of film quality and the increase of cell coupling rate become obstacles to enhancement of a degree of integration of the flash memory device.
As a result, research has been conducted on development of a new memory device having a non-volatile memory characteristic and an effective structure for enhancing the degree of integration, which have yielded a representative phase change memory device. A unit cell of the phase change memory device includes an access device and a data storage element serially connected to the access device. The data storage element has a bottom electrode electrically connected to the access device and a phase change material layer in contact with the bottom electrode. The phase change material layer is one which is electrically switched between an amorphous state and a crystalline state or between several resistivity states under the crystalline state based on the amount of current applied thereto.
FIG. 1 is a partial cross-sectional view schematically illustrating a conventional phase change memory device, and FIG. 2 is a plan view illustrating an active contact surface of a phase change material layer in a conventional phase change memory device.
Referring to FIGS. 1 and 2, a typical phase change memory device includes a lower interlayer insulating layer 12 disposed in a predetermined region of a semiconductor substrate 1, a lower interconnection 10 disposed within the lower interlayer insulating layer 12, an upper interlayer insulating layer 13 covering the lower interconnection 10, an upper interconnection 18 disposed on the upper interlayer insulating layer 13, a phase change material pattern 16 disposed within the upper interlayer insulating layer 13, a bottom electrode 14 electrically connected between the phase change material pattern 16 and the lower interconnection 10, and a top electrode 17 electrically connected between the phase change material pattern 16 and the upper interconnection 18.
When a program current flows through the bottom electrode 14, Joule heat is generated at an interface 20 (hereinafter, referred to as ‘active contact surface’) between the phase change material layer 16 and the bottom electrode 14. The Joule heat transforms a portion 22 (hereinafter, referred to as an ‘active volume portion’) of the phase change material pattern 16 to an amorphous or crystalline state. A resistivity of the active volume portion 22 having the amorphous state is higher than that of the active volume portion 22 having the crystalline state. Accordingly, by detecting a current flowing through the active volume portion 22 in a read mode, information stored in the unit cell of the phase change memory device may be discriminated as a logical one (1) or logical zero (0).
In this case, the program current should be increased in proportion to increased size of the active contact surface 20. The access device should be designed so as to have sufficient current drivability to supply the program current. However, in order to enhance the current drivability, the area occupied by the access device is increased. That is, it is advantageous to improve the degree of integration of the phase change memory device by decreasing the size of the active contact surface 20. In addition, it is required to optimize the volume of the active volume portion 22.
A method for decreasing the active contact surface 20 is disclosed in U.S. Pat. No. 6,514,788 B2 entitled “Method for manufacturing contacts for a chalcogenide memory device” to Quinn.
FIG. 3 is an intermediate process plan view illustrating a method of forming a contact for a chalcogenide memory device disclosed in U.S. Pat. No. 6,514,788 B2, and FIG. 4 is a process cross-sectional view taken along the line X-X of FIG. 3.
Referring to FIGS. 3 and 4, the method of forming the contact of the chalcogenide memory device includes forming a first oxide layer on a predetermined region of a semiconductor substrate and forming a via hole within the first oxide layer. A metal conductor 35 covering sidewalls of the via hole is deposited and then a second oxide layer 34 filling the via hole is formed. A third oxide layer is formed to cover a predetermined region on the metal conductor 35. A silicon nitride spacer 39 is formed on sidewalls of the third oxide layer, and the third oxide layer is removed. The metal conductor 35 is etched using the silicon nitride spacer 39 as a mask to form a bottom electrode. As a result, the bottom electrode which has a size smaller than a limit of a photolithography process may be formed.
When the phase change material pattern 16 is formed to be larger than the bottom electrode 14 as shown in FIGS. 1 and 2, the active volume portion 22 is formed in a hemisphere. That is, the effect of decreasing the active volume portion 22 may be reduced based on the size and the arrangement shape of the phase change material pattern 16 even when the size of the bottom electrode 14 is decreased to minimize the active contact surface 20.
In conclusion, a technique of optimizing the size and the arrangement shape of the phase change material pattern 16 as well as decreasing the size of the bottom electrode 14 is required.